FPGA Acceleration by Dynamically-Loaded Hardware Libraries
In DTU Compute Technical Report-2016, 2016
Abstract
Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs.
Info
Report, 2016
In DTU Compute Technical Report-2016, 2016
UN SDG Classification
DK Main Research Area
Science/Technology
